IEEE ComSoC Oct Meeting

Date and Time

Wed. Oct 13, 2010, 6:00 - 8:00PM


National Semiconductor, Building E, Conference Room, 2900 Semiconductor Dr, Santa Clara, CA 95051


6:00 - 6:30pm
6:30 - 6:40pm
6:40 - 7:30pm
7:30 - 7:50pm
  Cheese,Crackers&Drinks and Networking
  Pannel Seesion / Q&A

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40/100 Gigabit Ethernet - Market needs, Applications, and Standards


John D\’Ambrosia, Director, Ethernet-Based Standards, CTO Office, Force10 Networks
Ilango Ganga, Server Communications Architect, LAN Access Division, Intel
Mark Gustlin, Principal Engineer, Cisco Systems

Moderator: Prasanta De, IEEE ComSocSCV Emerging Applications Director


As the Director, Ethernet-based Standards in the CTO Office at Force10 Networks, John D\’Ambrosia leads the company's involvement in industry groups. John has been an active participant in the development of Ethernet-related technologies since 1999. Recently, John served as the chair of the IEEE P802.3ba Task Force, which developed 40 Gb/s and 100 Gb/s Ethernet. Prior, John served as secretary for the IEEE 802.3ap Backplane Ethernet Task Force, and participated in the development of XAUI for 10 Gigabit Ethernet. John is a founder of the Ethernet Alliance and has served as a director and secretary. John was the chair of the XAUI Interoperability work group for the 10 Gigabit Ethernet Alliance. For all of his efforts related to Ethernet, John was recognized by Network World in 2006, as part of its "50 Most Powerful People in Networking" list. John also acted as secretary for the High Speed Backplane Initiative and chair of the Optical Internetworking Forum's Market Awareness & Education committee. Prior to joining Force10, John was with Tyco Electronics for 17 years.

Ilango Ganga is a Server Communications Architect at Intel’s LAN Access Division. Ilango is responsible for architecting next generation Ethernet technologies including higher speed Ethernet, I/O virtualization and data center communications for LAN controller products. Ilango has over 19 years of industry experience in the area of Ethernet communications, blade server networking, switch silicon development and has held various roles in hardware design, Engineering management, architecture, and product planning. Ilango is an active contributor to the Ethernet standards development including backplane Ethernet, data center bridging and edge virtual bridging. He recently served as the Chief Editor of the IEEE P802.3ba 40Gb/s and 100Gb/s Ethernet task force. Ilango has 7 patents pending in the area of networking technology.

Mark is a Principal Engineer in the Routing business unit at Cisco Systems. He is a systems architect and is one of the editors of the IEEE 802.3ba standard. Mark has over 20 years of experience in data and telecom system development. Mark holds a B.S. in Electrical Engineering from San Jose State University.


Ethernet\’s Next Evolution – 40GbE and 100GbE by John D\’Ambrosia

This talk will provide an overview of the Ethernet Eco-system and the applications within that drove the need for the development of IEEE Std. 802.3baTM-2010 40Gb/s and 100Gb/s Ethernet Standard. Technology trends in computing and network aggregation and their role in driving the market need for 40GbE and 100GbE will be discussed.

The IEEE Std 802.3ba-2010 40Gb/s and 100Gb/s Architecture by Ilango Ganga

This session provides an overview of IEEE Std 802.3ba-2010 40Gb/s and 100Gb/s Ethernet specifications, objectives, architecture and interfaces.
The next generation higher speed Ethernet addresses the needs of computing, aggregation and core networking applications with dual data rates of 40Gb/s and 100 Gb/s. The 40/100 Gigabit Ethernet (GbE) architecture allows flexibility, scalability and leverages existing 10 Gigabit standards and technology where possible. The IEEE Std 802.3ba-2010 provides physical layer specifications for Ethernet communication across copper backplane, copper cabling, single-mode and multi-mode optical cabling systems.
The 40/100 Gigabit Ethernet utilizes the IEEE 802.3 Media Access Control sublayer (MAC) coupled to a family of 40 and 100 Gigabit physical layer devices (PHY). The layered architecture includes multilane physical coding sublayer (PCS), physical medium attachment sublayer (PMA) and physical medium dependant sublayers (PMD) for interfacing to various physical media. It also includes an Auto-Negotiation sublayer (AN) and an optional forward error correction sublayer (FEC) for backplane and copper cabling PHYs. The optional management data input/output interface (MDIO) is used for connection between 40/100 GbE physical layer devices and station management entities. The architecture includes optional 40 and 100 Gigabit Media Independent Interfaces (XLGMII and CGMII) to provide a logical interconnection between the MAC and the Physical Layer entities. It includes 40 and 100 Gigabit attachment unit interfaces (XLAUI and CAUI), four or ten lane interface, intended for use in chip-to-chip or chip-to-module applications. It also includes a 40 and 100 Gigabit parallel physical interface (XLPPI and CPPI), four or ten lane non-retimed interface, intended for use in chip-to-module applications with certain optical PHYs. The presentation will also outline the applications for some of the above interfaces.

Physical Layer (PCS/PMA) Overview by Mark Gustlin, Principal Engineer, Cisco Systems

This paper describes the Physical Coding Sublayer (PCS) and the Physical Medium Attachment (PMA) for the 40-Gb/s and 100-Gb/s Ethernet interfaces currently under standardization within the IEEE 802.3ba task force. Both of these speeds will initially be realized with a parallel PMD approach which requires bonding multiple lanes together through a striping methodology. The PCS protocol has the following attributes: Re-uses the 10GBASE-R PCS (64B/66B encoding and scrambling), just running at 4x or 10x as fast to provide for all of the required PCS functions for the data which will traverse multiple PMD lanes. Part of the PCS is a striping protocol which stripes the data to the PMD lanes on a per 66 bit block basis in a round robin fashion. Periodically an alignment block is added to each PMD lane. This alignment block acts as a marker which allows the receive side to deskew all lanes in order to compensate for any differential delay that the individual PMD lanes experience. The PMA sublayer provides the following functions: Provides per input-lane clock and data recovery, bit level multiplexing to change the number of lanes, clock generation, signal drivers and optionally provides loopbacks and test pattern generation/checking.

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