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About Cavium 


Job title - Senior Verification Engineer
 

Job location: San Jose

Responsibilities:

  • Develop the architecture for a functional verification environment including reference models, bus functional monitors and drivers.
  • Write a verification test plan using random techniques and coverage analysis and working with designers to ensure it is complete.
  • Build a constrained random environment for various functional blocks as well as for full chip testing.
  • Develop tests and tune the environment to achieve the coverage goals.
  • Debug failures and work with the logic designers to resolve the issues.

Requirements:

  • BSCS/EE or equivalent required with 2-7 years of logic verification experience of functional units in Microprocessor-based SOC products.
  • Strong programming skills using C++ and Verilog.
  • Experience with writing a detailed test plan and building a sophisticated directed random verification environment.
  • Working knowledge in one or more of the following: Processor architecture, SOC components, SOC inter-connect busses and memory interfaces.
  • Experience in System Verilog is strongly desired.
  • Experience in working with EDA verification tools (e,g; waveform viewers, coverage tools etc.).
  • Coding in scripting languages like Perl, Python, Tcl & UNIX Shell etc.
  • Good understanding of Linux O.S. and networking protocols is a plus.
  • Diligent, detail-oriented, and willing to take initiative and handle assignments with minimal supervision.
  • Must possess good communication skills, self-driven individual and a good team player.

 
 
Contact:
 
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What is Cavium? Cavium (NASDAQ: CAVM) is a provider of highly integrated semiconductor processors that enable intelligent networking, communications, storage, video and security applications.
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